8237 DMA Controller

DMA Controller is capable of becoming the bus master and supervising a transfer between an I/O or mass storage interface and memory. While making a transfer, it must be able to place memory addresses on the bus and send and receive handshaking signals. 
	A DMA controller is designed to service one or more I/O or mass storage interfaces and each interface is connected to the controller by a set of conductors. A portion of a DMA controller for servicing a single interface is called a channel.
Each channel will have
Control Register
Status Register
Address Register 
Byte Count Register 

	When data are being put in or taken out from its control registers  by the CPU,it is acting a s slave.
	When it is in the control of the bus , it is acting as the master.
Initilalizing the controller consists of filling these registers with the beginning address of the memory address that is used  as a buffer and number of bytes to be transferred. 
For an input to memory, each time the interface has the data to transfer it makes a DMA request through DREQ PIN of the DMA chip. 
The controller then makes a bus request through HOLD pin of DMA . 
The CPU after completing the current instruction, relinquishes the control of the system bus and send the DMA  the bus grant signal through the HLDA pin of DMA. 
After receiving a bus grant , it puts the contents of the address register on the address bus, sends an acknowledge back to the interface of the device who has issued the memory operation throught the DACK pin of the DMA. 
It then issues the I/O read and memory write signals. The interface then puts the data on the data bus and drops its request. 
When the memory accepts the data it returns a ready signal to the controller, which then increments the address register
It then decrements the byte count
Then it drops its bus request
Upon the count reaching zero, the process stops and a signal is sent to the processor as an interrupt requestor to the interface to notify it that the transfers have terminated.
An output is similarly executed ,except that controller issues I/O write and memory read signals and the data are transferred in the other direction

			The 8237 includes  Control and status register and four channels.
Each channel contains a 
mode register
current address register
base address register
current byte counter
base byte counter
request flag and
mask flag

     Bit 5 of the mode register specifies whether the contents of the address register are to be incremented(0)or decremented(1) after each data transfer , thus determining the order in which the data is stored in the memory.
If bit 4 is 1 , then autoinitialization  is enabled.When the current address  and current byte count registers are initially loaded, their contents are also put in the base address and base byte count registers. If autoinitialization is enabled, the current registers are automatically reloaded from the base registers whenever the count goes to zero.







Each channel may be put in the one of the four modes with its current mode being determined by bits 7 and 6 of the channel’s mode register. The four possible modes are
Single Transfer mode or cycle stealing mode (01)
	Afer each transfer the controller will release the bus to the processor for at least one bus cycle, but will immediately begin testing for DREQ inputs and proceed to steal another cycle as soon as a DREQ line becomes active.
Block Transfer mode or burst transfer mode (10)
	The bus control is not released by the DMA until the entire block of  data  has been transferred.
Demand Transfer Mode (00)	
		This mode is similar to the block mode except that DREQ is tested after each transfer.If DREQ is inactive, transfers are suspended until DREQ once again becomes active, at which time the block transfer continues from the point at which it was suspended. This allows the interface to stop the transfer in the event that its device cannot keep up. This is due to memry latency or slow speed of the interface.

Cascade Mode(11)	
	In this mode 8237’s are cascaded.

				


	Block diagram in Glenn A Gibson.